• 2364063
  • Senior FPGA/ASIC designer

DESCRIPTION

  • As soon as possible
  • To be discussed
  • Senior FPGA/ASIC Designer

    ORTHOGONE Technologies Inc. is an engineering firm specializing in communications and networking systems, and offering first class embedded system design services for various industries such as telecommunications, aerospace and avionics, transportation, defense and security.

    Orthogone Technologies is looking for Senior FPGA/ASIC Designers. The candidates must have experience in the telecommunications and networking industry.


    MAIN RESPONSIBILITIES

    • Write complex modules' technical specifications according to the highest level of the defined requirements;
    • Provide support to the hardware design and software design teams to ensure that the systems are efficient, profitable and durable;
    • Code in RTL (Verilog / VHDL);
    • Verify test plans, simulations, and test coverage;
    • Synthesize and elaborate routing and placement constraint;
    • Perform formal verifications.


    REQUIREMENTS

    • Bachelor degree in Electrical, Computer Engineering or equivalent;
    • Minimum of seven (7) years of experience in FPGA / ASIC design;
    • Solid experience in RTL coding (Verilog / VHDL);
    • Experience with:
    • FPGA design and simulation tools (ModelSim, Altera Quartus, Xilinx ISE/Vivado, Synplify, etc.).
    • Laboratory test equipment tools (oscilloscope, logic analyser, etc.).
    • Script automation development.
    • Source code management tools (ClearCase, SourceSafe, SVN, etc.).
    • Excellent ability to adapt in a variety of environments and to use different methodologies;
    • Capacity to communicate ideas and efficient solutions to customer;
    • Supportive attitude towards others and ability to influence them positively;
    • Ability to establish priorities and estimate deadline;
    • Ability to solve problems;
    • Committed, creative, and curious;
    • Good communication skills (oral and written);
    • Bilingual (French and English).


    ASSETS

    • Master degree in Electrical Engineering or Computer Science
    • Experience with communication protocols (e.g. Ethernet, Interlaken, OTN, etc.)

Requirements

  • Essential - Bach degree in Electrical, Computer eng or equiv.
  • Essential - Minimum of 7 years experience in FPGA/ASIC
  • Essential - Solid experience in RTL coding (Verilog/VHDL)
  • Essential - Tools: ModelSim, Altera Quartus, Xilinx ISE/Vivado
  • Essential - Source code tools: ClearCase, SourceSafe, SVN

Knowledge and abilities

  • Essential - Ability to adapt: methodology and environ.
  • Essential - Establish priorities and estimate deadline
  • Essential - Problem solving
  • Essential - Positive attitude and ability to influence
  • Essential - Good communication skills and bilingual (Fr/En)

Company description

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